Decision Feedback Equalizers (DFEs) and Decision Feedback Sequence Estimators (DFSEs) are circuits commonly used in communication systems to mitigate the impact of Inter-Symbol Interference (ISI) on the performance of the system. As such these circuits have been used in communication circuits for a number of decades.
The DFSE equalizer uses trellis decoding to assist in the compensation of the received signal. The performance obtained by a DFSE is generally between that of a DFE and a Maximum Likelihood Sequence Estimator (MLSE) based system.
However as communication circuits continue to operate at faster and faster speeds the ability to implement DFEs and MLSEs using classical architectures is becoming increasingly difficult due to the critical path associated with these circuits. As such a need exists to develop novel ways to implement these types of circuits at high speeds.
Implementing ISI mitigation circuits in high-speed communications systems provides benefits in terms of system performance but is problematic in terms of circuit design. The inherent feedback path delay of classical DFE and DFSE circuits is becoming increasingly more challenging as data rates increase.
One approach to high speed operation is to separate critical path computations into first and second portions. The first portion includes computations performed in a DFE and a Multiple DFE element. The second portion includes computations performed in a Viterbi decoder. A set of tail coefficients is generated in the DFE and used to decode an input signal.
Another approach to improved performance uses two parallel paths. A first path includes windowing and a second path does not. The first path uses a DFE to reduce inter-bin-interference introduced by the windowing. Bin select logic is used to detect the ‘best’ of the two parallel paths. Techniques have been developed to provide design procedures for windows. One technique is applied to subsets of sub-channels and the shape of the window is adapted to the observed conditions.
Improvements in the speed performance of feedback equalizers are desirable. The speed improvement should not come at the expense of parameters such as power dissipation.